- Huawei proposes Tau Scaling Law as an alternative to slowing Moore’s Law
- LogicFolding architecture reduces signal delay through vertically stacked semiconductor circuit designs
- Traditional transistor shrinking faces growing physical and economic limitations across the semiconductor industry
For more than five decades, the semiconductor industry has relied on a simple and powerful prediction, Moore’s Law, which states that transistors on a chip double roughly every two years, has now hit serious physical and economic walls.
The global industry faces slowing geometric scaling and the steady erosion of cost-per-transistor benefits.
This common challenge has forced every major player to search for a new path forward, and at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Huawei’s He Tingbo proposed an alternative framework called the Tau (τ) Scaling Law.
A new guiding principle from Shanghai
According to Huawei, peers and colleagues have already nicknamed this approach “Her’s Law” in recognition of her leadership.
Rather than focusing on shrinking transistor dimensions, this principle prioritises the reduction of signal propagation delay.
Huawei believes that compressing the time constant τ can drive ongoing evolution across semiconductors and electronic systems.
The key technological breakthrough enabling this new law is a technique called LogicFolding.
Traditional chip design lays out all electronic components in a flat, 2D grid that limits how close circuits can sit – and LogicFolding instead breaks down the physical boundaries of conventional circuit layouts by shortening critical-path wiring dramatically.
It reduces the resistive and capacitive load that normally slows down signal propagation between transistors.
The result is a systematic compression of the time constant τ at both the circuit and chip levels simultaneously.
Huawei has abandoned the traditional 2D chip design in favour of a layered 3D architecture.
Think of this transition as moving from a single-story home to a multi-story building with efficient elevators – Huawei can now stack multiple planar circuits vertically, which creates room for more transistors while placing core components closer together.
The shorter transmission distances between circuits directly improve frequency and overall performance.
Practical results and future ambitions
Huawei claims it has already mass-produced 381 chips using this new scaling law across various industries.
The upcoming Kirin chips, scheduled for launch in autumn 2026, will be the first to adopt the LogicFolding architecture.
By 2031, the company expects its high-end designs to achieve a transistor density equivalent to 14 Å or 1.4 nm processes.
“We believe that openness and collaboration are key to driving ongoing progress in the semiconductor industry,” said He Tingbo
“No single company can independently find all the answers along the path of semiconductor evolution.”
Huawei has every incentive to project confidence, given its current restrictions from accessing advanced manufacturing tools from TSMC or buying Nvidia’s latest AI chips.
Whether the τ Scaling Law can genuinely outpace Moore’s Law over the next decade remains an open question.
Competing firms will likely treat this announcement with measured skepticism until real hardware reaches neutral test laboratories.
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